The present invention relates generally to the field of integrated circuits. More specifically, the present invention relates to integrated circuit packages and methods of manufacturing such packages.
Integrated circuits (ICs), such as ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). ICs also often include flash memory cells. Such devices typically include a silicon, silicon-germanium, or other semiconductor substrate, above which are provided any of a variety of structures, such as vias, conductive lines, capacitors, resistors, isolation structures, contacts, interconnects, etc.
Flip chip integrated circuit packages utilize integrated circuits in an orientation that allows for relatively simple connection of the integrated circuits to the substrate. The integrated circuits are arranged face down on a substrate (e.g., an organic or ceramic substrate material) such that the active circuitry provided on a top surface of the integrated circuit is electrically connected (e.g., soldered) in contact with features provided in the substrate. In this manner, the features (i.e., the active circuitry) provided on the top surface of integrated circuit are aligned with the appropriate features on the underlying substrate. One advantageous feature of utilizing flip chip packaging is that the necessity to electrically connect the integrated circuit to the underlying substrate using wire bonding or another technique is eliminated. Another advantageous feature is that the overall size of the integrated circuit may be reduced as compared to packages that require wire bonding connections between the integrated circuit and the underlying substrate.
FIG. 1 is a schematic cross-sectional view showing a portion 10 of a conventional flip chip integrated circuit package. Portion 10 includes a substrate 20 having an integrated circuit 30 electrically connected thereto. Integrated circuit 30 is connected to substrate 20 using solder balls 32 or another method.
Substrate 20 includes a core 22 provided between a first buildup layer 24 and a second buildup layer 26. Buildup layers 24 and 26 include a variety of circuits and/or other components. Core 22 comprises an organic or ceramic material and a number of metal features (e.g., copper, aluminum) (not shown) for electrically connecting attached integrated circuits to other portions of the package.
One difficulty with the arrangement shown in FIG. 1 is that thermal stresses may be induced following the processing of the package. For example, the substrate comprises an organic material having a coefficient of thermal expansion (CTE) that is between approximately 17 and 20 ppm/° C. while the substrate is typically made of a semiconductor material such as silicon, silicon-germanium, gallium arsenide, or other III-V semiconductor materials. The integrated circuit conventionally has a CTE that is between approximately 2 and 3 ppm/° C. During processing of the package, the temperature of the package is approximately 170° C. After processing is completed, the temperature of the package returns to room temperature, at which point the substrate contracts more than the integrated circuit coupled thereto. The result of the thermally induced shrinkage differential between the substrate and the integrated circuit is that a stress is induced in the package that may ultimately cause a defect in the package. For example, a bending moment may be induced in the package that causes the components of the package (e.g., the integrated circuit or die and the substrate) to bend into a convex shape, which may cause cracks to develop at the interface at which the integrated circuit is coupled to the substrate. In such a case, electrical connections between the integrated circuit in the substrate may be compromised, resulting in a device which may not function in an expected manner.
It would be advantageous to provide an improved integrated circuit package (e.g., a flip chip package) that is configured to resist or compensate for thermally induced stresses in the package. It would also be advantageous to provide an integrated circuit package that utilizes commonly available materials to produce an integrated circuit package that resists thermally induced stresses. It would also be advantageous to provide a method of producing an integrated circuit package that resists thermally induced stresses.